8. Consider a three-bit register with the ability to parallel load a value or decrement by one. To implement the decrement capability use three half subtractors HSUB. The half subtractor truth table with inputs ai(bit in), bi (borrow in) and outputs bo (borrow out), do (bit out) is as follows. Three half subtractors are used to make a decrementer with positive logic enable input ena. The following function table summarizes the behavior of the register.

Fig: 1

Fig: 2

Fig: 3

Fig: 4

Fig: 5