Part III Instead of creating a memory module by using the BASIC FUNCTION etc., we can implement the required memory by specifying its structure in System Verilog code. In a System

Verilog-specified design it is possible to define the memory as a multidimensional array. A 32 x 4 array, which has 32 words with 4 bits per word, can be declared by the statement logic [3:0] memory_array [31:0]; In the FPGAs, such an array can be implemented either by using the flip-flops that each logic element contains or, more efficiently, by using the built-in memory blocks. 13/nPerform the following steps: Create a new Quartus project. 2. Write a System Verilog file that provides the necessary functionality, including the ability to load the RAM and read its contents as was done in task 2. 1. 3. Assign the pins on the FPGA to connect to the switches and the 7-segment displays. Compile the circuit and download it into the DE1_SOC. 5. Test the functionality of your design by applying some inputs and observing the output. Demo your results by direct presentation to instructor. 4./nPart IV The RAM block in Figurela has a single port that provides the address for both read and write operations. For this task you will create a different type of memory module, in which there is one port for supplying the address for a read operation, and a separate port that gives the address for a write operation. Perform the following steps. 1. Create a new Quartus project for your circuit. To generate the desired memory module open the IP Catalog and select the RAM: 2-PORT module in the Basic Functions On Chip Memory category. Choose "With one read port and one write port" in the category called "How will you be using the dual port ram?" a. Configure the memory size, clocking method, and registered ports the same way as in intro above. Go to Output above./n