ECE 2123L Digital Systems Laboratory Laboratory Assignment #6: State Machines – Vending Machine Circuit Design A. Pre-Lab B. In-Lab Exercises There is no pre-lab assignment for Lab 6. B.1. Vending Machine Background For the lab, you will design a circuit for a vending machine, where the problem description is given in section B.2. The final design/implementation of the circuit will use DFFs, logic gates, and the 4-bit binary to seven-segment-display circuit. Three switches will be utilized to select the input of a nickel, dime, or quarter, a button will be utilized as the clock input, and one switch will be used as a reset (reset on LOW input). The input to the vending machine will be entered on the switches, the clock button will be pressed, the state will update, and the outputs will be displayed on the seven-segment display and the LEDs. The LEDs will indicate the vending of the machine and the change returned (a different LED for nickel, dime, or two dimes). The seven- segment display will be used to indicate the amount of change deposited in the machine. This design should result in 10 states to indicate the amount of change in the machine, and you should use one-hot encoding (meaning 10 flip-flops). In addition to the state machine, you will need to design state to binary logic for the ones and tens digits of the deposits. To assist you with the design of the state to binary circuit, consider the design of a truth table that maps state to the binary value for the ten's digit and the one's digit. Note that some bits will always be zero and that there are likely a lot of repeating patterns in the resulting table. B.2. Vending Machine Specification Specification of the Problem: You have been enlisted to design a soda machine dispenser for your department lounge. Sodas are partially subsidized by the student chapter of the IEEE, so they cost only 25 cents. The machine accepts nickels, dimes, and quarters. When enough coins have been inserted, it dispenses the soda and returns any necessary change. Design an FSM controller for the soda machine. The FSM inputs are Nickel, Dime, and Quarter, indicating which coin was inserted. Assume that exactly one coin is inserted on each cycle. The outputs are Dispense, ReturnNickel, ReturnDime, and ReturnTwoDimes. When the FSM reaches at least 25 cents (recall that the amount of deposited change should be the current state, so it moves to the 25 cent or greater state on the clock cycle), it asserts Dispense and the necessary Return outputs required to deliver the appropriate change. Then after a clock cycle it should be ready to start accepting coins for another soda (all states resulting in dispense and/or change will then return to state 0). ECE 2123L Digital Systems Laboratory B.3. Paper Design of Vending Machine Design the state machine diagram, the state transition tables, the flip-flop (current state) input equations, the output equations, and the state to binary digit (binary encoding) equations. You do not need to draw the schematics. You and your partner should individually submit the design that you have developed as a team during the lab. B.4. Verilog Design of Flip Flop SystemVerilog is a hardware description language (HDL) used to model digital circuits and sys- tems. It is typically used for design, simulation, and verification of digital circuits, ranging from the simplest to highly complex systems with millions of gates. Here are some of the fundamental concepts you need to understand when using Verilog: Modules: A module is the primary building block in Verilog. It can represent anything from a simple gate to a complex subsystem. Each module has a name and a port list, which includes inputs, outputs, and possibly inouts. module AND GATE ( input wire a, input wire b, output wire c ); assign c = a & b; endmodule Data Types: ECE 2123L Digital Systems Laboratory The list of data types available in System Verilog Data-type 2-state/4-state # Bits signed/unsigned C equivalent reg 4 >= 1 unsigned CV wire 4 >= 1 unsigned integer 4 32 32 signed S real double Y STEM M time realtime VERI011 VERI071 G double CV logic 4 >= 1 unsigned bit 2 >= 1 unsigned byte 2 00 8 signed char shortint 2 16 signed short int int 2 32 signed int longint 2 64 signed long int shortreal float Resources: https://www.chipverify.com/systemverilog/systemverilog-datatypes Continuous Assignments: These are used to model combinational logic. The assign keyword is used for this. It assigns the output as the continuous evaluation of an expression. assign output = input1 & input2%;B // AND operation Procedural Assignments: These are used to model sequential logic. The always keyword is used to specify conditions under which the block of code will execute. The begin and end key- words denote the start and end of an always block. always @(posedge clk) begin end q <= d; // Flip-flop Testbenches: These are modules written to simulate and test other modules. They typically do not have any inputs or outputs, but instead instantiate the module under test and apply stimuli to its inputs to observe and verify its behavior. ECE 2123L Digital Systems Laboratory In-Lab Assignment Let's look at a full adder. A full-adder has three inputs; A, B, Cin and produces two outputs; Cout and Sum. Here is a simple representation of a full adder in System Verilog: module fullAdder (A, B, cin, sum, cout); input logic A, B, cin; output logic sum, cout; assign sum = A^ B^ cin; assign cout = A&B | cin & (A^B); endmodule // test bench module fullAdder_testbench(); logic A, B, cin, sum, coutl fullAdder dut (A, B, cin, sum, cout); initial begin //test condition similar to a waveform input A = 0; B = 0; cin = 0; #10; cin = 1; #10; B = 1; cin = 0; #10; cin = 1; #10; A = 1; B = 0; cin = 0; #10; B = cin 1; cin = 1; #10; = 0; #10; cin = 1; #10; end //initial endmodule In this System Verilog module, the D flip-flop is sensitive to the positive edge of the clock signal clk or the positive edge of the reset signal reset. If reset is high, it sets the output q to 0. If not, it sets q to the value of d at the rising edge of clk. 1. Watch this YouTube video to guide you with this implementation. 2. Use the System Verilog code above to represent a full adder and the testbench. A simplified code for the test condition is available in the Appendix. 3. Simulate the module in ModelSim 4. Include the code and simulation screenshot at the end of the lab. 5. No lab report is needed for this lab. Appendix: ECE 2123L Digital Systems Laboratory Simplified code for the testbench condition using for loop. integer i; initial begin for(i=0; i<2**3;i++) begin {A, B, cin} = i; #10; end //for loop end //initial