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Q1: A2Write down the value for signalY', given A = 8'b11110111 and the following Verilog continuous assignment: See Answer
Q2: Given the following two values: Y = 8'b10010111 H =8 b10101010 Write down the result of the following assignment: See Answer
Q3: Referring to Fig. A19, write down a pair of input combinations, which if applied to the logic circuit inputs in sequence, would reveal the timing hazard.See Answer
Q4: Figure B3a shows a data exchange system that uses a single-bit shared bus line(SB) to pass digital information from a set of data transmitters, 'AQA3 and CO..C3',to data receivers 'B0..B3 and DO.D3'. All signals are 1-bit, apart from SA, SB, SCand SD, which are 2-bit (indicated by the 'x' enclosed within the terminal symbols). The two multiplexers (MUXS) at top-left and bottom-right of Fig. B3a use 2-bit select inputs 'SA' and 'SC' to choose a transmit channel (03). Similarly, the two de-multiplexers (DMXS) at top-right and bottom-left of Fig. B3a use 2-bit select inputs"SB' and 'SD' to choose a receive channel (03). Choose either the MUX or DMX and sketch a gate-level logic circuit implementation of the symbol (MUX or DMX). Depending upon which choice you made above, write down the Verilog-HDL description of the other symbol, Le if you sketched the logic circuit for the MUX (DMX), write down the Verilog description of the DMX (MUX). In your descriptions, you may make use of continuous assignment statements and/or primitive gate instantiations.(6 morke) Write down the name of the Verilog-HDL built-in primitive element that could be used to model the four three-state buffers connected to the shared bus 'SB', in Fig. B3a. Write down the values, in Verilog format, of the following control signals: SA, SB, SC, SD, ENA and ENB In order to perform the following data transfer operations in Fig. B3a: i.Transmit data from A3 to B1. Figure B3b shows a particular type of counter based on a shift register. The asynchronous set (S) and reset (R) inputs of the flip-flops are active-high, assume any unconnected inputs are at logic-0. (2 marks)Sketch a set of digital waveforms for the outputs, <Q3, Q2, Q1, Q0>, of the counteralong with the clock input 'CIK. Assume the circuit has previously been reset bypulsing the Rst input to logic-1. (6 marks)Given that the frequency of the clock input 'Çlk' is 10 MHz, deduce the frequency of any Q output.See Answer
Q5: Figure A5 shows a cascade of multiplexers. When S is logic-0, the output Y is driven by the upper input (0), and when S is logic-1 the output is driven by the lower input(1). Write down an equivalent Verilog continuous assignment for Fig. A5. See Answer
Q6: With reference to Fig. A8, write down the name of the Verilog-HDL primitive element for components labelled 'T1' and T2'.See Answer
Q7: Figure A19 shows the K-Map of a sum-of-products logic circuit showing thegroupings used to form the products. Write down the type of static hazard present in the sum-of-products circuit.See Answer
Q8: 5. Use a synchronous 4-bit binary up counter (with load and enable) to design a modulo-8counter (also called offset counter) that begins with 0100, which means the counting sequence is: 0100->0101->0110->0111->1000->1001->1010->1011->0100-0101... Please complete your design using the figure need. on the next page. Use some logic gates if you need See Answer
Q9: (Q.2) Tiny Power System, that you developed in Assignment 1 has a control center and 3 substations, all of them connected through the SCADA system. Although the system is small, all 3 substations are installed with an Intelligent Electronic Device (IED). Each substation has 2 circuit breakers on the 2 transmission lines connecting the other 2 substations.Develop a detailed model of the cyber system deployed on the Tiny Power system using a software tool (similar to the ICT models described in [1]). Describe your model in a 2-page report. Specify sources of cyber vulnerabilities and explain how your model can be used for simulation of the impact of cyber attacks.See Answer
Q10: (Q1) Prepare a short report about key differences between electrons flow in the electric grid(considering electrons will not cross transformers) and data packets flow in the SCADA system.Develop a table comparing source, sink, control devices, control mechanisms and protocols followed in these systems for electrons/ data packets?See Answer
Q11: Pre-scaling by 8 means the configuration register of the timer will be divided into 8 bits the counting frequency of the timer will be divided by 8 the counting frequency of the timer will be multiplied the maximum count of the timer will be multiplied by 8.See Answer
Q12: Explain the need for state minimization (2 marks) A synchronous, sequential system is represented by the state table below Minimize the state table using an implication chart . Hence, draw an equivalent, but minimal state table and the minimized state diagram|. See Answer
Q13: Write a Boolean expression for the output Z with respect to the given inputs Use a PLA array like that given in Figure 3 to implement the multiplexer function Consider a 2 to 1 multiplexer with positive logic enable ea and select input ai described by the following function table.See Answer
Q14: 3. T flip - flop T flip-flop works as follows: if the input T = 0, the output stays the same; if the input T =1,the output toggles. In other words, the characteristic equation for the T flip-flop is Q+= TOQ. a) Complete the following state transition table for the T flip-flop. b) Complete the following timing diagram for the T flip-flop. Assuming Q=0 at the beginning. See Answer
Q15: Explain the characterestic curve of a Varistor(Minimum 5 sentences) shown below. ReferTrg Notes Page No-32 See Answer
Q16: QUESTION 2Realize the following functions using AND and OR gates. Assume that there are norestrictions on the number of gates which can be cascaded and minimize the number ofgate inputs. (a) AC'D + ADE' + BE' + BC' + A'D'E' (b) AE + BDE + BCE + BCFG + BDFG + AFGSee Answer
Q17: QUESTION 6Design a minimum three-level NOR-gate circuit to realize f = a'b' + abd + acdSee Answer
Q18: 3. We discussed in class about electromagnetic interference and performed related experiments in our lab. Suppose you are designing a medical device to acquire a bio signal that has frequency components between 1 and 500 Hz. The device will be used in an environment that is susceptible to a very high 60 Hz electromagnetic interference. What is your approach to minimize the interference without distorting the bio signal been measured? You must explain your answer. (20 pts) Be specific, clear, direct and succinct in your questions.See Answer
Q19: An operational amplifier is shown in Figure 2. The op-amp has the following specifications: Input resistance Rin= 1M ohms Output resistance Ro= 200ohms Open-loop gain Ao = 100,000. Unity Gain Bandwidth = 5MHZ a) i. Sketch the real circuit model for the amplifier. ii.write down the KCL equation at inverting terminal onthe circuit model write down the KCL equation at the output terminal on the circuit modelii. b) Draw a typical open-loop frequency response in (dB) for the op-amp. Indicate the open-loop DC gain, cut-off frequency and Unity Gain Frequency. (c) Determine the closed-loop bandwidth of the amplifier. The input signal is V(t)=0.1 \cdot \sin \left(2 \pi \times 500 \times 10^{3} t\right) V The output signal is V_{o}(t)=V_{-} \cdot \sin \left(2 \pi \times 500 \times 10^{3} t\right) V Determine the amplitude Vm of the output signal.See Answer
Q20: How Much Do You Remember About Filter Design (1 Design a simple, discrete-time filter with the following properties IIR, causal, and stable H\left(e^{j \omega}\right)=0 \text { at } \omega=\{0.85 \pi, 0.9 \pi, 0.95 \pi\} H\left(\mathrm{e}^{j \omega}\right) \text { has a resonant peak at } \omega=0.2 \pi The filter should have a notch at 1/9 Use the smallest filter order that meets the requirements. Choose a value for r (and a different value of r for the notch) and determine the gain that is needed to make Write an expression for H(2) and show the pole-zero plot. Roughly sketch what H(e) lookslike.See Answer

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